1. Field of the Invention
The present invention relates to a semiconductor device; and, more particularly, to a pulse generator for providing a pulse signal with a constant pulse width regardless of variations in a pulse width and period of an external clock.
2. Description of Related Art
Generally, a pulse generator is widely used in a synchronous memory device such as a synchronous dynamic random access memory (SDRAM) operating in synchronization with an external clock.
FIG. 1 (Prior Art) is a schematic diagram showing a conventional pulse generator 10, and FIG. 2 is a timing diagram explaining the operation of pulse generator 10 shown in FIG. 1.
Pulse generator 10 includes an inverter INV11 for inverting an external clock CLK_IN to generate an inverted clock, a delay unit 110 for delaying the inverted clock for a predetermined time and an output unit 120 for receiving the external clock CLK_IN and an output of the delay unit 110 to generate a pulse signal CLK_OUT. The pulse signal CLK_OUT has a pulse width corresponding to the predetermined time.
When a logic high period of the external clock CLK_IN is shorter than a delay period of the delay unit 110, a pulse width of the pulse signal CLK_OUT gets also short.
Accordingly, since the pulse width of the pulse signal is changed according to the pulse width and period of the external clock CLK_IN, it is difficult to achieve stable operation of internal circuits.
This invention provides a pulse generator for generating a pulse signal having a constant pulse width regardless of variations in a pulse width and period of an external clock.
In accordance with an aspect of the present invention, there is provided a pulse generator for providing a pulse signal with a constant pulse width. An an edge detection means, coupled between a node and a ground terminal, detects an edge of an external clock to set a node to a predetermined level. A delay means selectively delays the voltage level of the node according to the voltage level of the node. A post-charge means charges the node in response to an output of the delay means. An input control means controls the transfer of a next external clock according to the output of the delay means and the external clock. An output means receives the voltage level of the first node and generates the pulse signal.